Indexed ports

Syside Bug Reports
1

I am trying to get indexed ports working but seem to be failing.

ref port GPIO : Interfaces::GPIOPort[32];

ref connection TEST1 connect andGate.OUT to soc.GPIO[1];
ref connection TEST2 connect soc.GPIO[2] to andGate.IN1;

Seems to be a problem with the CLI-Parser?! Trying to use syside viz:
Unexpected reserved keyword ‘[’, expected one of [“SINGLE_LINE_NOTE”, “[”, “$”, “NAME”, “(”, “ElementReference”, “MULTILINE_NOTE”, “MultiplicityRange”, “OwningMembership”, “ReferenceSubsetting”, “Feature”, “Feature”, “OwningMembership”, “FeatureChaining”, “EndFeatureMembership”, “Feature”].

Any hint what I am doing wrong?

2

Hi Steven,

I believe you are mixing up the syntax. soc.GPIO [1] would not mean “the first element from GPIO list” like it may do in programming languages. Instead, with this syntax you are trying to set the soc.GPIO multiplicity to “1”, which is not supported in this particular connection use case.

For referring to an element in a list, you need to use #(i) syntax. This is called an Index expression and its description can be found in section 7.4.9.3 of KerML spec.

Index expression. An index expression specifies the invocation of the indexing function # from the BaseFunctions library model (see 9.4.2). The default behavior for this function is given by the specializationSequenceFunctions::'#', for which the first operand is expected to evaluate to a sequence of values, and the second operand is expected to evaluate to an index into that sequence. Default indexing is from 1 using Natural numbers. Note that parentheses are required around the second operand.

sensors#(activeSensorIndex)

However, that is not enough in your case. In your case, you should also modify the model like so (I don’t have the full model, so I am inventing a bit):

package StevenForumPost {
    occurrence def Context {
        part andGate {
            port OUT;
            port IN1;
        }

        port def GPIOPort;
        part soc {
            ref port GPIO : GPIOPort [32];
            gpio1 = GPIO#(1);  // <- Here I say `gpio1` is my first pin
            gpio2 = GPIO#(2);
        }

        ref connection TEST1 connect andGate.OUT to soc.gpio1; // <- here I connect to that pin
        ref connection TEST2 connect soc.gpio2 to andGate.IN1;
    }
} // package StevenForumPost
3

Thank you for the hints, that helps me quite a lot. Sorry for asking basic questions, too.
This does not work for creating diagrams in CLI, where it is a direct connection between a port of a part and the port of another part, right? It will just create in the diagram a separate connection block showing this connection, but not connecting two parts directly.

4 
       ref port GPIO : GPIOPort [32];

FYI, the “ref” keyword is unnecessary since the port usages are always referential.

Regarding visualization, if you make gpio1/2 usages not just reference usages, but port usages, then Modeler CLI will show it. Also I recommend making port GPIO usage abstract, so that it is clear that in itself these 32 pins are placeholders and need further specialization

        part soc {
            abstract port GPIO : GPIOPort [32];
            port gpio1 = GPIO#(1); 
            port gpio2 = GPIO#(2);
        }